Virtual machine is a concept put forward and put into practice by IBM Corporation in the 60's of the 20th century, when mainframes were the mainstream computers. A mainframe was divided into multiple virtual machines and virtual machine monitors (VMMs) were used for compartmentation so that a variety of applications or a plurality of users could share this scarce resource.
However, with the reduction of cost in hardware and the enhancement of computing capabilities as well as the emergence of a multi-task operating system (OS), VMMs gradually step down from the stage of history, while microcomputers and personal computers (PCs) are becoming increasingly popular.
Nevertheless, as virtual machines are powerful and successful in that users may access to and use those functions and equipment that can be formed simply through a combination of instruction sets. In recent years, virtual machine monitors have once again become a focus in the academic circle and industry circle. Virtual machine monitors provide a virtual solution for the limitation of the modern computer system architecture, making it a powerful tool which will greatly enhance the capacity of modern computer systems.
Today's complex instruction set computing (CISC) processor architecture, such as the X86 instruction set-based CISC processor architecture, holds a dominant position in many applications, i.e., the X86 instruction set-based CISC processor architecture is used in many large-sized server-based service applications. In order to enable server-based service applications to be widely run on a reduced instruction set computing (RISC) architecture-based microprocessor, it has been a necessary task to realize its compatibility with CISC processors. In addition, in the existing CISC processor-based computers, the applications are more diverse and plenty of commercial software is based on the CISC processor. So, in order to run a wider range of diverse applications on a RISC microprocessor, it's also very urgent to realize the compatibility of the RISC microprocessor with the CISC processor.
As a major branch of RISC processors, the MIPS instruction set-based RISC processor currently has many open-source virtual machine platforms capable of realizing a heterogeneous support from the MIPS instruction set-based RISC processor to an X86 instruction set-based CISC processor.
Many aspects need be taken into account if a virtual machine is used to make an X86 instruction set-based CISC processor compatible with an MIPS instruction set-based RISC processor. One aspect is the use of flag bits of the EFLAGES in the X86 instruction set-based CISC processor.
The flag register (EFLAGS) in the X86 instruction set mainly includes the following three parts of contents:                1. status Flags, including a total of 6 bits, which are CF (carry flag), PF (parity flag), AF (auxiliary flag), ZF (zero flag), SF (sign flag) and OF (overflow flag);        2. DF (direction flag) for controlling the direction of a string operation instruction; and        3. other system flags and I/O privilege level (IOPL), including single-step mode flag, interrupt enable, I/O priority and so on, which cannot be modified by a user program.        
The fixed-point operating instruction of the X86 instruction set supports the operation of a total of 6 bits (CF bit, PF bit, AF bit, ZF bit, SF bit and OF bit) of the flag bits of a flag register (EFLAGS). That is to say, in addition to data values, many operating instructions will also generate flag bits of a flag register, thereby enabling some transfer instructions to use the flag bits as a transfer condition to realize an instruction jump.
However, in the RISC processor-based X86 virtual machine in the prior art, the operation of 6-bit flag bits of a flag register is performed via simulation, which will be a considerable overhead and cause a great impact on the performance.